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[Data structs] cf_fft_2048_18

Description: 2048点的fft的算法源程序，应用verilog编程实现。-2048 point fft algorithm source code, application programming Verilog.
Platform: | Size: 1575936 | Author: 罗伟 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: fpga功能实现有限字长响应FIR 用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
Platform: | Size: 139264 | Author: 吴务 | Hits:

[MacOS develop] firVerilog

Description: 里面是一个FIR滤波器的VHDL语言 具体的功能里面有详细的介绍 对毕业设计者很有帮助的 -There is a FIR filter VHDL language specific features which are detailed introduction to the graduate designers helpful
Platform: | Size: 4096 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] FIR_verilog

Description: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形-Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform
Platform: | Size: 628736 | Author: yejianchao | Hits:

[Communication-Mobile] suAra6Rm

Description: fir滤波器的Verilog程序,看看吧，还不错！-fir filter Verilog procedures, take a look at it, but also good!
Platform: | Size: 4096 | Author: wanghua | Hits:

[VHDL-FPGA-Verilog] firOK

Description: 17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真-17FIR 瞬 VHDL 爰?说 牡 苑
Platform: | Size: 1029120 | Author: fangyingjie | Hits:

[VHDL-FPGA-Verilog] fir6dlms

Description: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Platform: | Size: 1024 | Author: 李允 | Hits:

[VHDL-FPGA-Verilog] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真-Verilog-based filtering of fir and bring matlab simulation
Platform: | Size: 24576 | Author: 宇天 | Hits:

[VHDL-FPGA-Verilog] 16_FIR

Description: 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
Platform: | Size: 799744 | Author: yuming | Hits:

[DSP program] fir

Description: 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
Platform: | Size: 1024 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] fir_Verilog

Description: 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
Platform: | Size: 5120 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] fir_16

Description: fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
Platform: | Size: 742400 | Author: zhc | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[VHDL-FPGA-Verilog] coeff_rom_0_7

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_1_6

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_3_4

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
Platform: | Size: 324608 | Author: simeon chan | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:
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